Many integrated circuits today are fabricated using complementary metal-oxide silicon (CMOS) processes. For example, semiconductor fabrication facilities (fabs) for producing CMOS monolithic circuits are relatively common, particularly for use in foundry arrangements where a xe2x80x9cfablessxe2x80x9d developer wishes to have their circuit designs created in an integrated circuit. Moreover, CMOS processes are relatively inexpensive and typically produce a high yield as compared to some other integrated circuit fabrication processes.
CMOS devices which are available using common CMOS processes include N-type (NMOS) and P-type (PMOS) devices. PMOS devices may be preferred for use in providing switchable selection of circuits, such as under control of a digital controller, due to their resistance to premature switching as compared to NMOS devices. Moreover, PMOS devices may be desirable for use in providing a controlled current source due to their reduced resistance as compared to an NMOS device of similar size and configuration.
In addition to the above mentioned device types, bipolar devices may also be available when using a bi-CMOS process. Such bipolar devices typically include NPN-type devices and PNP-type devices. Bipolar devices generally exhibit superior noise performance as compared to the aforementioned PMOS devices and even NMOS devises. Bipolar devices are often desirable for use in resonators or voltage controlled oscillators due to the need for good noise performance.
The use of CMOS processes to provide electronic components is not, however, without disadvantage. For example, PMOS devices are often noisy, particularly in the low frequency ranges, such as in the range from approximately 100 Hz to approximately 1 MHz. Accordingly, a circuit implementing a PMOS device, such as to provide a current source, may experience the introduction of noise associated with the PMOS device. Although bipolar devices have much superior noise performance than do PMOS devices, the lateral PNP bipolar devices (which are typically available in most BiCMOS technologies) may not provide a suitable current source, e.g., the efficiency and/or the size of the device may not meet design preferences. Moreover, it is often difficult to provide an acceptable match between a PMOS device and a bipolar devices in particular circuit configurations, or portions thereof, thereby suggesting the use of a PMOS device in some situations.
Accordingly, integrated circuits may be developed utilizing PMOS devices, for which noise filtering is desired. For example, a voltage controlled oscillator circuit may be developed in an integrated circuit using CMOS processes in which a PMOS transistor is utilized in providing a current source. A circuit providing bypass filtering of the bias noise associated with the use of a PMOS transistor current source may include an inductor and capacitor (LC) filter network. A capacitor utilized in such a filtering circuit may be relatively large, such as on the order of 1 xcexcF. However, substrate space in such integrated circuits is typically limited and, therefore, must be utilized efficiently. Accordingly, it may be desirable to utilize a discrete capacitor and/or other filter circuit components, in order to efficiently utilize substrate area.
However, a competing concern is the availability of external leads (pins) from an integrated circuit package. For example, as large scale integration is utilized in providing an integrated circuit, the physical size of the integrated circuit, and therefore its packaging, becomes smaller while the number of signals provided thereto/therefrom increases. Accordingly, efficient use should be made of integrated circuit external leads.
Accordingly, a need exists in the art for systems and methods which provide for efficient filtering of noise associated with the use of particular components in an integrated circuit.
A further need exists in the art for such systems and methods to provide optimized use of integrated circuit external leads.
The present invention is directed to systems and methods which provide a common bypass node with respect to multiple circuits of an integrated circuit. According to a preferred embodiment, a circuit for filtering bias noise introduced by components of the integrated circuit may be coupled to this common bypass node and bypass bias filtering may be provided with respect to each of the multiple circuits. According to a preferred embodiment, the common bypass node is associated with an external lead or pin of the integrated circuit to thereby facilitate the efficient use of integrated substrate area as well as the efficient use of external interfaces thereof.
For example, according to a most preferred embodiment of the present invention, an integrated circuit provides multiple voltage controlled oscillators (VCOs), such as to provide a wide range of oscillator frequencies through use of a series of oscillators each providing controlled oscillation in a portion of the wide range of oscillator frequencies. Bias current to the multiple VCOs is preferably provided through a node common to each VCO circuit. For example, a common current source may be provided with respect to the multiple VCOs, whereby switching circuitry may be utilized in selecting one or more VCOs to which current from the current source is to be provided at any particular point in time. The common node is preferably utilized for coupling a bypass filter circuit to thereby provide bypass bias noise filtering with respect to each VCO.
A most preferred embodiment bypass filter circuit comprises a LC filter network. A capacitor utilized in such a LC filter network is expected to be relatively large, such as on the order of 1 xcexcF, and therefore is preferably implemented external to the preferred embodiment integrated circuit. For example, a discrete capacitor may be coupled to an external lead or pin of the aforementioned integrated circuit to thereby provide an inexpensive solution which optimizes the use of integrated circuit substrate area. Moreover, as the preferred embodiment utilizes a common node for each VCO, the use external interfaces in providing bypass bias noise filtering is minimized.
Additionally, the common bypass node of the preferred embodiment may be utilized in providing cooperative operation of the multiple circuits coupled thereto. For example, where the aforementioned single current source is used to provide bias current multiple VCOs, the common node coupling may be utilized in splitting the current for simultaneous operation of multiple VCOs.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention.